Hmm i feel like doing some thing useful ..so i thought of making a blog for my vlsi interview ...it might be useful for me and others ..provide others with links to other good blogs ..and of course i will not be organised ..i will be posting every thing randomly  when ever i find something useful  ....


Ok lets start ..i'm posting some useful links for interview preparation .. I'm very thankful to these guys who took the pain to write these .. its very helpful ..and i would says its necessary for all those who are preparing for interviews . Because how ever you prepare for the interview , reading books ,your notes ,projects, video lectures   finally what happens is the interviewer starts with the basics and he just want to know how you can present it . So you should really know how to present your knowledge to him . It's the presentation that is more important on a phone interview . Ok here are the links that i'm going through now ...

http://www.asic.co.in/Index_files/Digital_interview_questions1.htm

http://www.systemverilog.in/digital.php

http://vlsi-expert.blogspot.com/2011/02/timing-analysis-basis-what-and-why.html

i will keep on posting them as i go on my road of preparation ...

Ho i forgot ....i just finished going through the video lectures of Rabaey ... here is a link to a uses full site with lot of video lectures ..

http://video.ac/electrical-engineering-141-professor-jan-m-rabaey-uc-berkeley/

Using Digital Clock Managers (DCMs)

Summary

Digital Clock Managers (DCMs) provide advanced clocking capabilities to Spartan-3 Generation FPGA applications (Spartan-3, Spartan-3E, Spartan-3A, Spartan-3AN, and Spartan-3A DSP families). Primarily, DCMs eliminate clock skew, thereby improving system performance. Similarly, a DCM optionally phase shifts the clock output to delay the

incoming clock by a fraction of the clock period. DCMs optionally multiply or divide the incoming clock frequency to synthesize a new clock frequency. The DCMs integrate directly with the FPGA’s global low-skew clock distribution network. 

Introduction

DCMs integrate advanced clocking capabilities directly into the FPGA’s global clock distribution network. Consequently, DCMs solve a variety of common clocking issues, especially in high-performance, high-frequency applications: • Eliminate Clock Skew, either within the device or to external components, to improve overall system performance and to eliminate clock distribution delays. • Phase Shift a clock signal, either by a fixed fraction of a clock period or by incremental amounts.

• Multiply or Divide an Incoming Clock Frequency or synthesize a completely new frequency by a mixture of clock multiplication and division.

• Condition a Clock, ensuring a clean output clock with a 50% duty cycle.

• Mirror, Forward, or Rebuffer a Clock Signal, often to deskew and convert the incoming clock signal to a different I/O standard—for example, forwarding and converting an incoming LVTTL clock to LVDS.

• Any or all the above functions, simultaneously.