Friday, May 11, 2012

i forgot about this blog ....

http://only-vlsi.blogspot.com/



 What is slack?
'Slack' is the amount of time you have that is measured from when an event 'actually happens' and when it 'must happen'.. The term 'actually happens' can also be taken as being a predicted time for when the event will 'actually happen'.
When something 'must happen' can also be called a 'deadline' so another definition of slack would be the time from when something 'actually happens' (call this Tact) until the deadline (call this Tdead).
Slack = Tdead - Tact.
Negative slack implies that the 'actually happen' time is later than the 'deadline' time...in other words it's too late and a timing violation....you have a timing problem that needs some attention.





Difference between heap and stack?

The Stack is more or less responsible for keeping track of what's executing in our code (or what's been "called"). The Heap is more or less responsible for keeping track of our objects (our data, well... most of it - we'll get to that later.).
Think of the Stack as a series of boxes stacked one on top of the next. We keep track of what's going on in our application by stacking another box on top every time we call a method (called a Frame). We can only use what's in the top box on the stack. When we're done with the top box (the method is done executing) we throw it away and proceed to use the stuff in the previous box on the top of the stack. The Heap is similar except that its purpose is to hold information (not keep track of execution most of the time) so anything in our Heap can be accessed at any time. With the Heap, there are no constraints as to what can be accessed like in the stack. The Heap is like the heap of clean laundry on our bed that we have not taken the time to put away yet - we can grab what we need quickly. The Stack is like the stack of shoe boxes in the closet where we have to take off the top one to get to the one underneath it.



Difference between mealy and moore state machine?

A) Mealy and Moore models are the basic models of state machines. A state machine which uses only Entry Actions, so that its output depends on the state, is called a Moore model. A state machine which uses only Input Actions, so that the output depends on the state and also on inputs, is called a Mealy model. The models selected will influence a design but there are no general indications as to which model is better. Choice of a model depends on the application, execution means (for instance, hardware systems are usually best realized as Moore models) and personal preferences of a designer or programmer
B) Mealy machine has outputs that depend on the state and input (thus, the FSM has the output written on edges)
Moore machine has outputs that depend on state only (thus, the FSM has the output written in the state itself.
Adv and Disadv
In Mealy as the output variable is a function both input and state, changes of state of the state variables will be delayed with respect to changes of signal level in the input variables, there are possibilities of glitches appearing in the output variables. Moore overcomes glitches as output dependent on only states and not the input signal level.
All of the concepts can be applied to Moore-model state machines because any Moore state machine can be implemented as a Mealy state machine, although the converse is not true.
Moore machine: the outputs are properties of states themselves... which means that you get the output after the machine reaches a particular state, or to get some output your machine has to be taken to a state which provides you the output.The outputs are held until you go to some other state Mealy machine:
Mealy machines give you outputs instantly, that is immediately upon receiving input, but the output is not held after that clock cycle.


How to achieve 180 deree exact phase shift?
Never tell using inverter
a) dcm's an inbuilt resource in most of fpga can be configured to get 180 degree phase shift.
b) Bufgds that is differential signaling buffers which are also inbuilt resource of most of FPGA can be used.


 What is significance of ras and cas in SDRAM?
SDRAM receives its address command in two address words.
It uses a multiplex scheme to save input pins. The first address word is latched into the DRAM chip with the row address strobe (RAS).
Following the RAS command is the column address strobe (CAS) for latching the second address word.Shortly after the RAS and CAS strobes, the stored data is valid for reading.


Tell some of applications of buffer?
a)They are used to introduce small delays
b)They are used to eliminate cross talk caused due to inter electrode capacitance due to close routing.
c)They are used to support high fanout,eg:bufg

http://www.edaboard.com/thread116973.html







Hmm i feel like doing some thing useful ..so i thought of making a blog for my vlsi interview ...it might be useful for me and others ..provide others with links to other good blogs ..and of course i will not be organised ..i will be posting every thing randomly  when ever i find something useful  ....


Ok lets start ..i'm posting some useful links for interview preparation .. I'm very thankful to these guys who took the pain to write these .. its very helpful ..and i would says its necessary for all those who are preparing for interviews . Because how ever you prepare for the interview , reading books ,your notes ,projects, video lectures   finally what happens is the interviewer starts with the basics and he just want to know how you can present it . So you should really know how to present your knowledge to him . It's the presentation that is more important on a phone interview . Ok here are the links that i'm going through now ...

http://www.asic.co.in/Index_files/Digital_interview_questions1.htm

http://www.systemverilog.in/digital.php

http://vlsi-expert.blogspot.com/2011/02/timing-analysis-basis-what-and-why.html

i will keep on posting them as i go on my road of preparation ...

Ho i forgot ....i just finished going through the video lectures of Rabaey ... here is a link to a uses full site with lot of video lectures ..

http://video.ac/electrical-engineering-141-professor-jan-m-rabaey-uc-berkeley/



Using Digital Clock Managers (DCMs)
Summary
Digital Clock Managers (DCMs) provide advanced clocking capabilities to Spartan-3 Generation FPGA applications (Spartan-3, Spartan-3E, Spartan-3A, Spartan-3AN, and Spartan-3A DSP families). Primarily, DCMs eliminate clock skew, thereby improving system performance. Similarly, a DCM optionally phase shifts the clock output to delay the
incoming clock by a fraction of the clock period. DCMs optionally multiply or divide the incoming clock frequency to synthesize a new clock frequency. The DCMs integrate directly with the FPGA’s global low-skew clock distribution network. 
Introduction
DCMs integrate advanced clocking capabilities directly into the FPGA’s global clock distribution network. Consequently, DCMs solve a variety of common clocking issues, especially in high-performance, high-frequency applications: • Eliminate Clock Skew, either within the device or to external components, to improve overall system performance and to eliminate clock distribution delays. • Phase Shift a clock signal, either by a fixed fraction of a clock period or by incremental amounts.
• Multiply or Divide an Incoming Clock Frequency or synthesize a completely new frequency by a mixture of clock multiplication and division.
• Condition a Clock, ensuring a clean output clock with a 50% duty cycle.
• Mirror, Forward, or Rebuffer a Clock Signal, often to deskew and convert the incoming clock signal to a different I/O standard—for example, forwarding and converting an incoming LVTTL clock to LVDS.
• Any or all the above functions, simultaneously.